With finer structuring of the circuit patterns formed on semiconductor wafers, defects that occur in their manufacturing processes are causing increasingly significant effects to product yields, and it is becoming more and more important to control the manufacturing processes so that no such defects arise during the manufacturing phase. Currently at semiconductor wafer-manufacturing sites, defect inspection devices are generally used to improve yields. In mass-production lines for semiconductor manufacture, it is necessary to properly monitor an occurring state of defects during the manufacturing processes. This requires inspecting wafers as many as possible using a defect inspection device.
Defect inspection devices use optical means or an electron beam to represent a state of a wafer surface in the form of an image and automatically process this image for rapid identification of defect positions on the wafer. In such a defect inspection device, since the rapidness of the identification is crucial, a pixel size of the images acquired is maximized, that is, resolution is minimized, to reduce the amount of image data to be acquired. In many cases, even when existence of defect candidates can be confirmed from a detected image of such low resolution, the defect candidates are difficult to discriminate in detail from defects that are to be actually detected.
Prior art relating to functions and the like of such a defect inspection device is disclosed in JP-A-2003-6614 (Patent Document 1). Patent Document 1 describes the configuration, defect inspection function, and operational sequence of the defect inspection device.
In addition, a method of fixed-point inspection is available to detect defects by first acquiring one pixel value for each of a plurality of images acquired by sequentially imaging predefined regions-of-interest of dies during electron beam scanning with a scanning electron microscope (SEM), and then comparing this pixel data with defect discrimination threshold levels. Prior art associated with such method is disclosed in JPA-2005-150727 (Patent Document 2).